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vishay siliconix dg528, dg529 document number: 70068 s11-1029?rev. d, 23-may-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 latchable single 8-ch/different ial 4-ch analog multiplexers features ? low r ds(on) : 270 ? ? 44 v power supply rating ? on-board address latches ? break-before-make ? low leakage - i d(on) : 30 pa benefits ? improved system accuracy ? microporcessor bus compatible ? easily interfaced ? reduced crosstalk applications ? data acquisition systems ? automatic test equipment ? avionics and military systems ? medical instrumentation description the dg528 is an 8-channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (a 0 , a 1 , a 2 ). dg529, a 4-channel dual analog multiplexer, is designed to connect one of four differential inputs to a common differential output as determined by its 2-bit binary address (a 0 , a 1 ) logic. these analog multiplexers have on-chip address and control latches to simplify design in microprocessor based applica- tions. break-before-make switching action protects against momentary shorting of the in put signals. the dg528/529 are built on the improved plus-40 cmos process. a buried layer prevents latchup. the on chip ttl-compatible address latches simplify digital interface design and reduce board space in data acquisition systems, process contro ls, avionics, and ate. functional block diagram and pin configuration wr d rs s 8 a 0 a 1 en a 2 v- gnd s 1 v+ s 2 s 5 s 3 s 6 s 4 s 7 dual-in-line decoders/drivers 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11 top view 910 latches en a 2 v gnd s 1 v+ s 2 s 5 s 3 s 6 plcc 14 15 16 17 18 8 7 6 5 4 1 2 319 20 11 10 913 12 top view 4 d nc 8 7 a wr nc rs a latches decoders/drivers 0 1 s s s dg528 dg528 wr d a rs d b a 0 a 1 en gnd v- v+ s 1a s 1b s 2a s 2b s 3a s 3b s 4a s 4b dual-in-line decoders/drivers 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11 top view 910 latches dg529
www.vishay.com 2 document number: 70068 s11-1029?rev. d, 23-may-11 vishay siliconix dg528, dg529 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 truth tables and ordering information logic "0" = v al ?? 0.8 v logic "1" = v ah ?? 2.4 v x = don?t care notes: a. signals on s x , d x or in x exceeding v+ or v- will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 6.3 mw/c above 75 c. d. derate 12 mw/c above 75 c. e. derate 10 mw/c above 75 c. truth table - dg528 8-channel single-ended multiplexer a 2 a 1 a 0 en wr rs on switch latching x x x x 1 maintains previous switch condition reset x x x x x 0 none (latches cleared) transparent operation x x x 0 0 1 none 0 0 0 1 0 1 1 0 0 1 1 0 1 2 0 1 0 1 0 1 3 0 1 1 1 0 1 4 1 0 0 1 0 1 5 1 0 1 1 0 1 6 1 1 0 1 0 1 7 1 1 1 1 0 1 8 ordering information - dg528 temp range package part number 0 c to 70 c 18-pin plastic dip dg528cj 20-pin plcc dg528dn - 25 c to 85 c 18-pin cer dip dg528bk - 55 c to 125 c dg528ak dg528ak/883 5962-8768901va truth table - dg529 differential 4-channel multiplexer a 0 en wr rs on switch latching x x 1 maintains previous switch condition reset x x x 0 none (latches cleared) transparent operation x 0 0 1 none 0 1 0 1 1 1 1 0 1 2 0 1 0 1 3 1 1 0 1 4 ordering information - dg529 temp range package part number 0 c to 70 c 18-pin plastic dip dg529cj - 25 c to 85 c 18-pin cer dip dg529bk - 55 c to 125 c dg529ak/883 absolute maximum ratings parameter symbol limit unit voltages referenced to v- v+ 44 v gnd 25 digital inputs a , v s , v d (v-) - 2 to (v+) + 2 or 30 ma, whichever occurs first current (any terminal except s or d) 30 ma continuous current, s or d 20 peak current, s or d (pulsed at 1 ms, 10 % duty cycle max) 40 storage temperature (ak, bk suffix) - 65 to 150 c (cj, dn suffix) - 65 to 125 power dissipation (package) b 18-pin plastic dip c 470 mw 18-pin cerdip d 900 20-pin plcc e 800
document number: 70068 s11-1029?rev. d, 23-may-11 www.vishay.com 3 vishay siliconix dg528, dg529 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, no t subject to production test. f. v in = input voltage to perform proper function. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications a parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 15 v, wr = 0, rs = 2.4 v, v in = 2.4 v, 0.8 f f temp. b typ. c a suffix - 55 c to 125 c b, c, d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full - 15 15 - 15 15 v drain-source on-resistance r ds(on) v d = 10 v, i s = - 200 a room full 270 400 500 450 550 ? greatest change in r ds(on) between channels f ? r ds(on) - 10 v < v s < 10 v room 6 % source off leakage current i s(off) v en = 0 v, v d = 10 v v s = 10 v room full 005 - 1 - 50 1 50 - 5 - 50 5 50 na drain off leakage current i d(off) v en = 0 v, v d = 10 v v s = 10 v dg528 room full 0.015 - 10 - 200 10 200 - 20 - 200 20 200 dg529 room full 0.008 - 10 - 100 10 100 - 20 - 100 20 100 drain on leakage current i d(on) v s = v d = 10 v v en = 2.4 v dg528 room full 0.03 - 10 - 200 10 200 - 20 - 200 20 200 dg529 room full 0.015 - 10 - 100 10 100 - 20 - 100 20 100 digital control logic input current i ah v a = 2.4 v room hot - 0.002 - 10 - 30 - 10 - 30 a input voltage high v a = 15 v room hot 0.006 10 30 10 30 logic input current input voltage low i al v en = 0 v, 2.4 v, v a = 0 v rs = 0 v, wr = 0 v room hot - 0.002 - 10 - 30 - 10 - 30 dynamic characteristics transition time t trans see figure 5 room 0.6 1 s break-before-make interval t open see figure 4 room 0.2 en and wr tu r n - o n t i m e t on(en,wr) see figure 6 and 7 room 1 1.5 en and wr turn-off time t off(en,rs) see figure 6 and 8 room 0.4 1 charge injection q v s = 0 v, r y = 0 ??? c l = 10 ? f room 4 pc off isolation oirr v en = 0 v, r l = 1 k ??? c l = 15 pf v s = 7 v rms , f = 500 khz room 68 db logic imput capacitance c in f = 1 mhz room 2.5 pf source off capacitance c s(off) v en = 0 v, v d = 0 v, f = 140 khz room 5 drain off capacitance c d(off) v en = 0 v, v d = 0 v f = 140 khz dg528 room 25 dg529 room 12 minimum input timing requirements write pulse width t w full 300 300 ns a x , en data set up time t s full 180 180 a x , en data hold time t h full 30 30 reset pulse width t rs v s = 5 v, see figure 3 full 500 500 power supplies positive supply current i+ v en = v a = 0 v room 2.5 2.5 ma negative supply current i- room - 1.5 - 1.5
www.vishay.com 4 document number: 70068 s11-1029?rev. d, 23-may-11 vishay siliconix dg528, dg529 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless noted) r ds(on) vs. v d and power supply input switching threshold vs. v+ and v- supply voltages - 20 - 15 - 10 - 5 0 5 10 15 20 500 400 300 200 100 v d ? drain v oltage (v) 7.5 v r ds(on) ? drain-source on-resistance ( ) 10 v 15 v 20 v t a = 25 c 2.5 2.0 1.5 1.0 0.5 0 v+, v- positive and negative supplies (v) t a = 25 c (v) t v 0 5 10 15 20 leakage currents vs. analog voltage supply currents vs. toggle frequency - 15 - 10 - 5 0 5 10 15 0 - 20 - 40 - 60 i d(off) i d(on) i s(off) 15 v supplies t a = 25 (pa) i , i sd v analog ? analog voltage (v) i+, i- (ma) 1 k 10 k 100 k 1 m 4 3 2 1 0 i+ i- toggle frequency (hz)
document number: 70068 s11-1029?rev. d, 23-may-11 www.vishay.com 5 vishay siliconix dg528, dg529 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 schematic diagram (typical channel) detailed description the internal structure of the dg528/dg529 includes a 5-v logic interface with input protection circuitry followed by a latch, level shifter, decoder and finally the switch constructed with parallel n- and p-channel mosfets (see figure 1). the logic interface circuit compares the ttl input signal against a ttl threshold reference voltage. the output of the comparator feeds the data inpu t of a d type latch. the level sensitive d latch conti nuously places the d x input signal on the q x output when the wr input is low, resulting in transpar- ent latch operation. as soon as wr returns high, the latches hold the data last present on the d x input, subject to the mini- mum input timing requirements. following the latches the q x signals are level shifted and decoded to provide proper drive levels for the cmos switches. this level shifting insures full on/off switch operation for any analog signal present bet ween the v+ and v- supply rails. the en pin is used to enable the address latches during the wr pulse. it can be hard-wired to the logic supply or to v+ if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. the rs pin is used as a master reset. all latches are cleared regardless of the state of any other latch or control line. the wr pin is used to transfer the state of the address control lines to their latches, except during a reset or when en is low (see truth tables). figure 1. v+ v+ v+ latches en clk reset a x wr rs v ref d o d n q o q n level shift v+ v- v- v- v- gnd v- v+ d v- v+ decode s 1 v- v+ v- v+ v+ s n figure 2. 3 v 0 3 v 0 50 % 80 % 80 % en t w t s t h wr a 0 , a 1 , (a 2 ) figure 3. 3 v 0 0 50 % t rs t off (rs) rs 80 % v o switch output
www.vishay.com 6 document number: 70068 s11-1029?rev. d, 23-may-11 vishay siliconix dg528, dg529 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 4. break-before-make dg528 dg529 en v+ gnd v- + 5 v 35 pf - 15 v + 15 v + 2.4 v rs a 0 , a 1 , (a 2 )d b , d all s and d a wr 300 v o 50 logic input switch output v o v s t open t r < 20 ns t f < 20 ns 3 v 0 v 50 % 80 % 0 v figure 5. transition time dg528 dg529 s 1b s 1a - s 4a , d a s 2b and s 3b d b rs a 0 a 1 50 wr 300 v o 10 v 10 v s 4b en v+ gnd v- 35 pf - 15 v + 15 v + 2.4 v rs s 1 s 2 - s 7 a 0 a 1 a 2 50 wr 300 v o s 8 10 v 10 v en v+ gnd v- d 35 pf - 15 v + 15 v + 2.4 v 3 v 0 v logic input switch output v s8 v o t trans t r < 20 ns t f < 20 ns s 8 on s 1 on t trans 0 v v s1 50 % 10 % 90 %
document number: 70068 s11-1029?rev. d, 23-may-11 www.vishay.com 7 vishay siliconix dg528, dg529 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 6. enable t on/toff time dg528 dg529 rs en + 2.4 v s 1 s 2 - s 8 a 0 a 1 a 2 50 wr 300 v o v+ gnd v- d - 5 v 35 pf - 15 v + 15 v s 1b s 1a - s 4a , d a s 2b - s 4b rs d b a 0 a 1 50 wr 300 v o en + 2.4 v v+ gnd v- - 5 v 35 pf - 15 v + 15 v logic input switch output v o t r < 20 ns t f < 20 ns 3 v 0 v 0 v t off(en) t on(en) 50 % 90 % v o figure 7. write turn-on time t on(wr) 3 v 0 v 0 v 50 % dg528 dg529 wr switch output v o 20 % t on(wr) a 0 , a 1 , (a 2 ) d b , d en wr 300 w remaining switches s 1 or s 1b v o rs v+ gnd v- + 5 v 35 pf - 15 v + 15 v + 2.4 v
www.vishay.com 8 document number: 70068 s11-1029?rev. d, 23-may-11 vishay siliconix dg528, dg529 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 8. reset turn-off time t off(rs) 3 v 0 v 0 v 50 % dg528 dg529 rs switch output v o 80 % t off(rs) rs v o en remaining switches wr s 1 or s 1b d b , d a 0 , a 1 , (a 2 ) 300 w v+ gnd v- + 5 v 35 pf - 15 v + 15 v + 2.4 v figure 9. bus interface data bus reset address decoder address bus + 5 v en v+ v- d + 15 v - 15 v dg528 processor system bus 15 v analog inputs analog output wr rs s 1 s 8 a 0 , a 1 , a 2 , write
dg528, dg529 vishay general semiconductor document number: 70068 s11-1029?rev. d, 23-may-11 www.vishay.com 9 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. application hints are for design aid only, not guaranteed and not subject to production testing. b. electrical parameter chart based on v+ = 15 v, v- = - 15 v, v r = gnd. c. operation below 8 v is not recommended. the dg528/dg529 minimize the amount of interface hard- ware between a microprocessor system bus and the analog system being controlled or measured. the internal ttl com- patible latches give these mult iplexers write-only memory, that is, they can be programmed to stay in a particular switch state (e.g., switch 1 on) until the microprocessor determines it is necessary to turn different switc hes on or turn all switches off (see figure 9). the input latches becom e transparent when wr is held low; therefore, these multiplexers operate by direct command of the coded switch state on a 2 , a 1 , a 0 . in this mode the dg528 is identical to the popular dg508a. the same is true of the dg529 versus the popular dg509a. during system power-up, rs would be low, maintaining all eight switches in th e off state. after rs returned high the dg528 maintains all switches in the off state. when the sys- tem program performs a write operation to the address as- signed to the dg528, the a ddress decoder provides a cs active low signal which is gated with the write (wr) control signal. at this time the data on the data bus (that will deter- mine which switch to close) is stabilizing. when the wr signal returns to the high state, (pos itive edge) the input latches of the dg528 save the data from the data bus. the coded in- formation in the a 0 , a 1 , a 2 and en latches is decoded and the appropriate switch is turned on. the en latch allows all switc hes to be turned off under pro- gram control. this becomes us eful when two or more dg528s are cascaded to build 16-li ne and larger multiplexers. vishay siliconix maintains worldwide manufacturing capability. pro ducts may be manufactured at on e of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?70068 . application hints a v+ positive supply voltage (v) v - negative supply voltage (v) v in logic input voltage v inh(min) /v inl(max) (v) v s or v d analog voltage range (v) 20 - 20 2.4/0.8 20 15 b - 15 2.4/0.8 15 8 c - 8 (min) 2.4/0.8 8
e 1 e q 1 a l a 1 e 1 b b 1 l 1 s c e a d 12 3 18 package information vishay siliconix document number: 71231 02-jul-01 www.vishay.com 1
dim min max min max a 4.06 5.08 0.160 0.200 a 1 0.51 1.14 0.020 0.045 b 0.38 0.51 0.015 0.020 b 1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d 22.35 22.86 0.880 0.900 e 7.62 8.26 0.300 0.325 e 1 6.60 7.62 0.260 0.300 e 1 2.54 bsc 0.100 bsc e a 7.62 bsc 0.300 bsc l 3.18 3.81 0.125 0.150 l 1 3.81 5.08 0.150 0.200 q 1 1.27 2.16 0.050 0.085 s 0.76 1.52 0.030 0.060 0 15 0 15 ecn: s-03946?rev. d, 09-jul-01 dwg: 5313
0.101 mm 0.004 d?square d 1 ?square a 2 b 1 e 1 a 1 d 2 b a package information vishay siliconix document number: 71263 02-jul-01 www.vishay.com 1
dim min max min max a 4.20 4.57 0.165 0.180 a 1 2.29 3.04 0.090 0.120 a 2 0.51 ? 0.020 ? b 0.331 0.553 0.013 0.021 b 1 0.661 0.812 0.026 0.032 d 9.78 10.03 0.385 0.395 d 1 8.890 9.042 0.350 0.356 d 2 7.37 8.38 0.290 0.330 e 1 1.27 bsc 0.050 bsc ecn: s-03946?rev. c, 09-jul-01 dwg: 5306
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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